A typical implementation of ESD protection circuit technology is considered below. According to such a circuit, for example, an ESD protection circuit can suppress increases in additional capacitance of a signal terminal is disclosed in JP-A No. 2002-50698. In this circuit construction, a resistor element and a diode-connected (gate-source shorted) PMOS transistor 1 are placed between a signal terminal and a power supply line, a resistor element and a diode-connected NMOS transistor 2 are placed between the signal terminal and a ground (GND) line, and a diode connected NMOS transistor 3 is placed between the power supply line and the GND line. When an instantaneous high voltage is applied to the signal terminal, power consumed by the PMOS transistor 1 and the NMOS transistor 2 can be reduced by the resistor elements and the NMOS transistor 3. Consequently, the circuit can be made smaller and increases in additional capacitance of the signal terminal can be suppressed.
In a semiconductor chip, usually, an ESD protection circuit like the one disclosed in JP-A No. 2002-50698 is provided near an external signal terminal to prevent internal device destruction due to the application of an instantaneous high voltage or the like (hereinafter referred to as a surge) to the external signal terminal. Models of device destruction by this surge, a human body model, machine model, device charging model, etc. are widely known.
Meanwhile, for latest integrated circuit (IC) technologies that boost IC speed and reduce the component mounting area on a wiring board for product downsizing, a termination circuit may be provided in a semiconductor chip. Particularly, in a semiconductor chip having a data transfer speed of several hundred megabits per second to several gigabits per second, reflection waveforms occurring when data is transmitted through the chip become serious. For this reason, a termination circuit for impedance matching may be provided in the vicinity of an external signal terminal or between modules if a semiconductor chip consists of multiple modules.
Here, using an input circuit portion of such a semiconductor chip as an example, an example of its configuration is discussed. Referring to FIG. 13, which is a circuit diagram showing an example of the configuration of the input circuit portion of a semiconductor device. The semiconductor device shown in FIG. 13 is provided with an ESD protection circuit and a termination circuit on a signal node 1 on the line from a signal terminal IN to an input buffer Buf.
The ESD protection circuit is made up of, for example, a resistor element R7 and a diode D1 connected in series, placed between a supply voltage node VDD and the signal node ND1, and a diode D2 and a resistor element R8 connected in series, placed between the signal node ND1 and a reference voltage node VSS. The termination circuit is realized by, for example, a terminating resistor element Rt placed between the supply voltage node VDD and the signal node ND1. The diodes D1 and D2 may be replaced by diode-connected MOS transistors or other similar elements known to those possessing an ordinary skill in the pertinent arts, as is the case for the ESD protection circuit disclosed in JP-A No. 2002-50698.
However, when such a semiconductor chip comes to have an increasing number of signal terminals IN, die area increase will become a problem, because it is necessary to provide an ESD protection circuit and a termination circuit for each terminal. For example, if the termination circuit is provided by a resistor element, a relatively large die area is needed to form the resistor element on the semiconductor substrate. In recent years, there is an increasing need for higher-speed and smaller mobile devices and decreasing the die area is a crucial challenge.
Therefore a need exists to provide a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a smaller die area.